Abstract
For the first time, this brief analyzes the channel potential and capacitance in channel-stack type 3-D NAND flash memory structure. In addition, the effects of geometrical parameters on 3-D NAND flash design with gate-all-around and double-gate devices are studied. The model can be incorporated into a compact circuit model for 3-D NAND flash design optimization.
| Original language | English |
|---|---|
| Article number | 6913535 |
| Pages (from-to) | 3901-3904 |
| Number of pages | 4 |
| Journal | IEEE Transactions on Electron Devices |
| Volume | 61 |
| Issue number | 11 |
| DOIs | |
| State | Published - 1 Nov 2014 |
Keywords
- 3-D NAND flash memory
- capacitance modeling
- nanowire SONOS
- stacked array