TY - GEN
T1 - Presetting pulse-based flip-flop
AU - Kim, Chul Soo
AU - Kim, Joo Seong
AU - Kong, Bai Sun
AU - Moon, Yongsam
AU - Jun, Young Hyun
PY - 2008
Y1 - 2008
N2 - In this paper, presetting pulse-based flip-flop (PSPFF) is proposed. The flip-flop briefly presets its storage nodes to a medium voltage level between VDD and VSS just before input capturing. This presetting operation allows the proposed flip-flop to be faster and more clock-skew tolerant than conventional pulse-based flip-flops. Comparison results using a 80-nm CMOS process technology indicate that PSPFF has 22% improvement on clock-skew tolerance, 20% decrease of data-to-output delay, 22% reduction of power-delay product, and 21% reduction of layout area, as compared to PCSPFF.
AB - In this paper, presetting pulse-based flip-flop (PSPFF) is proposed. The flip-flop briefly presets its storage nodes to a medium voltage level between VDD and VSS just before input capturing. This presetting operation allows the proposed flip-flop to be faster and more clock-skew tolerant than conventional pulse-based flip-flops. Comparison results using a 80-nm CMOS process technology indicate that PSPFF has 22% improvement on clock-skew tolerance, 20% decrease of data-to-output delay, 22% reduction of power-delay product, and 21% reduction of layout area, as compared to PCSPFF.
UR - http://www.scopus.com/inward/record.url?scp=51749087277&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2008.4541486
DO - 10.1109/ISCAS.2008.4541486
M3 - Conference contribution
AN - SCOPUS:51749087277
SN - 9781424416844
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 588
EP - 591
BT - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
T2 - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Y2 - 18 May 2008 through 21 May 2008
ER -