Probability level dependence of failure mechanisms in Sub-20 nm NAND flash memory

Duckseoung Kang; Kyunghwan Lee; Myounggon Kang; Seongjun Seo; Dong Hua Li; Yuchul Hwang; Hyungcheol Shin

doi:10.1109/LED.2014.2301164

Probability level dependence of failure mechanisms in Sub-20 nm NAND flash memory

Duckseoung Kang, Kyunghwan Lee, Myounggon Kang, Seongjun Seo, Dong Hua Li, Yuchul Hwang, Hyungcheol Shin

School of Advanced Fusion Studies

Research output: Contribution to journal › Article › peer-review

9 Scopus citations

Abstract

We extracted final Δ V_th, time constant, and activation energy (E_a) of each mechanism in retention characteristics of sub-20-nm NAND flash main-chip according to the probability level (P level) of V_th cumulative probability distribution. As a result, we confirmed that at lower P level, the final Δ V_th of each mechanism increases sensitively according to P/E cycling stress. Temperature dependence of the final Δ V_th of each mechanism also increases with lowering P level, whereas trap-assisted tunneling (TAT) mechanism of corner area has complex characteristics on temperature. Interface trap recovery, TAT (plane), and TAT (corner) mechanism have larger E_a at high P level, whereas the E_a of detrapping mechanism decreases because of barrier lowering effect.

Original language	English
Article number	6730693
Pages (from-to)	348-350
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	35
Issue number	3
DOIs	https://doi.org/10.1109/LED.2014.2301164
State	Published - Mar 2014

Keywords

detrapping mechanism
failure mechanism
interface trap recovery
NAND flash memory
P level
temperature dependence
trap-assisted tunneling (TAT)

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10.1109/LED.2014.2301164

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title = "Probability level dependence of failure mechanisms in Sub-20 nm NAND flash memory",

abstract = "We extracted final Δ Vth, time constant, and activation energy (Ea) of each mechanism in retention characteristics of sub-20-nm NAND flash main-chip according to the probability level (P level) of Vth cumulative probability distribution. As a result, we confirmed that at lower P level, the final Δ Vth of each mechanism increases sensitively according to P/E cycling stress. Temperature dependence of the final Δ Vth of each mechanism also increases with lowering P level, whereas trap-assisted tunneling (TAT) mechanism of corner area has complex characteristics on temperature. Interface trap recovery, TAT (plane), and TAT (corner) mechanism have larger Ea at high P level, whereas the Ea of detrapping mechanism decreases because of barrier lowering effect.",

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author = "Duckseoung Kang and Kyunghwan Lee and Myounggon Kang and Seongjun Seo and Li, {Dong Hua} and Yuchul Hwang and Hyungcheol Shin",

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AU - Kang, Duckseoung

AU - Lee, Kyunghwan

AU - Kang, Myounggon

AU - Seo, Seongjun

AU - Li, Dong Hua

AU - Hwang, Yuchul

AU - Shin, Hyungcheol

PY - 2014/3

Y1 - 2014/3

N2 - We extracted final Δ Vth, time constant, and activation energy (Ea) of each mechanism in retention characteristics of sub-20-nm NAND flash main-chip according to the probability level (P level) of Vth cumulative probability distribution. As a result, we confirmed that at lower P level, the final Δ Vth of each mechanism increases sensitively according to P/E cycling stress. Temperature dependence of the final Δ Vth of each mechanism also increases with lowering P level, whereas trap-assisted tunneling (TAT) mechanism of corner area has complex characteristics on temperature. Interface trap recovery, TAT (plane), and TAT (corner) mechanism have larger Ea at high P level, whereas the Ea of detrapping mechanism decreases because of barrier lowering effect.

AB - We extracted final Δ Vth, time constant, and activation energy (Ea) of each mechanism in retention characteristics of sub-20-nm NAND flash main-chip according to the probability level (P level) of Vth cumulative probability distribution. As a result, we confirmed that at lower P level, the final Δ Vth of each mechanism increases sensitively according to P/E cycling stress. Temperature dependence of the final Δ Vth of each mechanism also increases with lowering P level, whereas trap-assisted tunneling (TAT) mechanism of corner area has complex characteristics on temperature. Interface trap recovery, TAT (plane), and TAT (corner) mechanism have larger Ea at high P level, whereas the Ea of detrapping mechanism decreases because of barrier lowering effect.

KW - detrapping mechanism

KW - failure mechanism

KW - interface trap recovery

KW - NAND flash memory

KW - P level

KW - temperature dependence

KW - trap-assisted tunneling (TAT)

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Probability level dependence of failure mechanisms in Sub-20 nm NAND flash memory

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