Program/erase model of nitride-based NAND-type charge trap flash memories

Doo Hyun Kim; Seongjae Cho; Dong Hua Li; Jang Gn Yun; Jung Hoon Lee; Gil Sung Lee; Yoon Kim; Won Bo Shim; Se Hwan Park; Wandong Kim; Hyungcheol Shin; Byung Gook Park

doi:10.1143/JJAP.49.084301

Program/erase model of nitride-based NAND-type charge trap flash memories

Doo Hyun Kim, Seongjae Cho, Dong Hua Li, Jang Gn Yun, Jung Hoon Lee, Gil Sung Lee, Yoon Kim, Won Bo Shim, Se Hwan Park, Wandong Kim, Hyungcheol Shin, Byung Gook Park

School of Electrical and Computer Engineering

Seoul National University

Research output: Contribution to journal › Article › peer-review

22 Scopus citations

Abstract

In this paper, we present a detailed study of the physical dynamics of the program/erase (P/E) operations in nitride-based NAND-type charge trapping silicon-oxide-nitride-oxide-silicon (SONOS) flash memories. By calculating the internal oxide fields, tunneling currents, and trapping charges, we evaluated the simple charge trapping mechanism. We calculated transient P/E threshold voltage (VT) shift considering the ONO fields and tunneling currents. All the parameters were obtained using totally physics-based equations with no fitting parameters or optimization steps. The results show conventional NAND SONOS flash memory P/E characteristics in the Fowler-Nordheim (FN) operation regime. Also, these P/E simulation results agree with the measurement data of 30 × 70nm² (L × W) SONOS flash memory devices that have 2.3/12/4.5 and 3/9/7nm ONO stack layers. This model fully accounts for the V_T shift as a function of the applied gate voltage, transient time, and thicknesses of silicon oxide and silicon nitride layers, which can be used for optimizing the ONO thicknesses and the parameters for improving performance.

Original language	English
Article number	084301
Journal	Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume	49
Issue number	8 PART 1
DOIs	https://doi.org/10.1143/JJAP.49.084301
State	Published - Aug 2010

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Kim, D. H., Cho, S., Li, D. H., Yun, J. G., Lee, J. H., Lee, G. S., Kim, Y., Shim, W. B., Park, S. H., Kim, W., Shin, H., & Park, B. G. (2010). Program/erase model of nitride-based NAND-type charge trap flash memories. Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 49(8 PART 1), Article 084301. https://doi.org/10.1143/JJAP.49.084301

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title = "Program/erase model of nitride-based NAND-type charge trap flash memories",

abstract = "In this paper, we present a detailed study of the physical dynamics of the program/erase (P/E) operations in nitride-based NAND-type charge trapping silicon-oxide-nitride-oxide-silicon (SONOS) flash memories. By calculating the internal oxide fields, tunneling currents, and trapping charges, we evaluated the simple charge trapping mechanism. We calculated transient P/E threshold voltage (VT) shift considering the ONO fields and tunneling currents. All the parameters were obtained using totally physics-based equations with no fitting parameters or optimization steps. The results show conventional NAND SONOS flash memory P/E characteristics in the Fowler-Nordheim (FN) operation regime. Also, these P/E simulation results agree with the measurement data of 30 × 70nm2 (L × W) SONOS flash memory devices that have 2.3/12/4.5 and 3/9/7nm ONO stack layers. This model fully accounts for the VT shift as a function of the applied gate voltage, transient time, and thicknesses of silicon oxide and silicon nitride layers, which can be used for optimizing the ONO thicknesses and the parameters for improving performance.",

author = "Kim, {Doo Hyun} and Seongjae Cho and Li, {Dong Hua} and Yun, {Jang Gn} and Lee, {Jung Hoon} and Lee, {Gil Sung} and Yoon Kim and Shim, {Won Bo} and Park, {Se Hwan} and Wandong Kim and Hyungcheol Shin and Park, {Byung Gook}",

year = "2010",

month = aug,

doi = "10.1143/JJAP.49.084301",

language = "English",

volume = "49",

journal = "Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers",

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publisher = "Japan Society of Applied Physics",

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AU - Kim, Doo Hyun

AU - Cho, Seongjae

AU - Li, Dong Hua

AU - Yun, Jang Gn

AU - Lee, Jung Hoon

AU - Lee, Gil Sung

AU - Kim, Yoon

AU - Shim, Won Bo

AU - Park, Se Hwan

AU - Kim, Wandong

AU - Shin, Hyungcheol

AU - Park, Byung Gook

PY - 2010/8

Y1 - 2010/8

N2 - In this paper, we present a detailed study of the physical dynamics of the program/erase (P/E) operations in nitride-based NAND-type charge trapping silicon-oxide-nitride-oxide-silicon (SONOS) flash memories. By calculating the internal oxide fields, tunneling currents, and trapping charges, we evaluated the simple charge trapping mechanism. We calculated transient P/E threshold voltage (VT) shift considering the ONO fields and tunneling currents. All the parameters were obtained using totally physics-based equations with no fitting parameters or optimization steps. The results show conventional NAND SONOS flash memory P/E characteristics in the Fowler-Nordheim (FN) operation regime. Also, these P/E simulation results agree with the measurement data of 30 × 70nm2 (L × W) SONOS flash memory devices that have 2.3/12/4.5 and 3/9/7nm ONO stack layers. This model fully accounts for the VT shift as a function of the applied gate voltage, transient time, and thicknesses of silicon oxide and silicon nitride layers, which can be used for optimizing the ONO thicknesses and the parameters for improving performance.

AB - In this paper, we present a detailed study of the physical dynamics of the program/erase (P/E) operations in nitride-based NAND-type charge trapping silicon-oxide-nitride-oxide-silicon (SONOS) flash memories. By calculating the internal oxide fields, tunneling currents, and trapping charges, we evaluated the simple charge trapping mechanism. We calculated transient P/E threshold voltage (VT) shift considering the ONO fields and tunneling currents. All the parameters were obtained using totally physics-based equations with no fitting parameters or optimization steps. The results show conventional NAND SONOS flash memory P/E characteristics in the Fowler-Nordheim (FN) operation regime. Also, these P/E simulation results agree with the measurement data of 30 × 70nm2 (L × W) SONOS flash memory devices that have 2.3/12/4.5 and 3/9/7nm ONO stack layers. This model fully accounts for the VT shift as a function of the applied gate voltage, transient time, and thicknesses of silicon oxide and silicon nitride layers, which can be used for optimizing the ONO thicknesses and the parameters for improving performance.

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Program/erase model of nitride-based NAND-type charge trap flash memories

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