Programmable VLSI neural network processor for digital communications

Joongho Choi, Sa Hyun Bang, Bing J. Sheu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

An analog VLSI neural network processor is developed for digital communication receiver applications without any need for a priori estimation of the channel characteristics. Network training is performed by the modified Kalman filtering algorithm to speed up the convergence process for inter-symbol interference and white Gaussian noise communication channels. The fabricated chip was based on a four-layered network running at 1 MHz in a 2-micrometer CMOS technology.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
PublisherPubl by IEEE
Pages16.5.1-16.6.4
ISBN (Print)0780308263
StatePublished - 1993
EventProceedings of the IEEE 1993 Custom Integrated Circuits Conference - San Diego, CA, USA
Duration: 9 May 199312 May 1993

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Conference

ConferenceProceedings of the IEEE 1993 Custom Integrated Circuits Conference
CitySan Diego, CA, USA
Period9/05/9312/05/93

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