Programmable-weight building blocks for analog VLSI neural network processors

Robert C. Chang, Bing J. Sheu, Joongho Choi, David Cheng Hsiung Chen

Research output: Contribution to journalArticlepeer-review

7 Scopus citations


Although the neural network paradigms have the intrinsic potential for parallel operations, a traditional computer cannot fully exploit it because of the serial hardware configuration. By using the analog circuit design approach, a large amount of parallel functional units can be realized in a small silicon area. In addition, appropriate accuracy requirements for neural operation can be satisfied. Components for a general-purpose neural chip have been designed and fabricated. Dynamically adjusted weight value storage provides programmable capability. Possible reconfigurable schemes for a general-purpose neural chip are also presented. Test of the prototype neural chip has been successfully conducted and an expected result has been achieved.

Original languageEnglish
Pages (from-to)215-230
Number of pages16
JournalAnalog Integrated Circuits and Signal Processing
Issue number3
StatePublished - 1996


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