TY - JOUR
T1 - SAECHAM
T2 - Secure and Efficient Lightweight Block Cipher CHAM Variant
AU - Shin, Myoungsu
AU - Shin, Hanbeom
AU - Kim, Insung
AU - Kim, Sunyeop
AU - Lee, Dongjae
AU - Hong, Deukjo
AU - Sung, Jaechul
AU - Hong, Seokhie
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2025
Y1 - 2025
N2 - The addition, rotation, XOR (ARX) structure, which comprises three fundamental operations—Addition, Rotation, and XOR—makes it well-suited for lightweight cryptography. To design a secure and efficient ARX cipher, it is necessary to find the optimal structure by properly combining the order, number of operations, and rotation amounts. CHAM64 is an ARX block cipher with a 64-bit block size, which is proposed as an attempt to enhance the lightweight characteristics of LEA . In this article, we present secure and efficient CHAM (SAECHAM), a variant of CHAM64 with a rearranged order of operations and adjusted rotation amounts. By changing the order of the operations in CHAM64 , six different CHAM -like structures can be created. We propose the properties that can be eliminated in the implementation process depending on the rotation amount in each structure. To improve suitability for constrained environments, such as 8-bit and 16-bit microcontrollers, we reduce the search space for rotation amounts and analyze the number of instructions. Using an SMT solver-based automatic search method, we analyze the security of 62 CHAM64 variants through differential and linear analysis. Among them, we find four variants with equal or better resistance to differential and linear cryptanalysis compared to CHAM64 . As a result, we propose the variant with the fewest instructions among them as SAECHAM . Through software implementations on 8-bit AVR, 16-bit MSP430, 32-bit ARM Cortex-M3 and Cortex-M4 platforms, we demonstrate that SAECHAM is efficient in terms of encryption speed and also performs efficiently when implemented using SIMD operations in high-performance CPUs.
AB - The addition, rotation, XOR (ARX) structure, which comprises three fundamental operations—Addition, Rotation, and XOR—makes it well-suited for lightweight cryptography. To design a secure and efficient ARX cipher, it is necessary to find the optimal structure by properly combining the order, number of operations, and rotation amounts. CHAM64 is an ARX block cipher with a 64-bit block size, which is proposed as an attempt to enhance the lightweight characteristics of LEA . In this article, we present secure and efficient CHAM (SAECHAM), a variant of CHAM64 with a rearranged order of operations and adjusted rotation amounts. By changing the order of the operations in CHAM64 , six different CHAM -like structures can be created. We propose the properties that can be eliminated in the implementation process depending on the rotation amount in each structure. To improve suitability for constrained environments, such as 8-bit and 16-bit microcontrollers, we reduce the search space for rotation amounts and analyze the number of instructions. Using an SMT solver-based automatic search method, we analyze the security of 62 CHAM64 variants through differential and linear analysis. Among them, we find four variants with equal or better resistance to differential and linear cryptanalysis compared to CHAM64 . As a result, we propose the variant with the fewest instructions among them as SAECHAM . Through software implementations on 8-bit AVR, 16-bit MSP430, 32-bit ARM Cortex-M3 and Cortex-M4 platforms, we demonstrate that SAECHAM is efficient in terms of encryption speed and also performs efficiently when implemented using SIMD operations in high-performance CPUs.
KW - AVR
KW - Addition
KW - CHAM
KW - Cortex-M3
KW - Cortex-M4
KW - MSP430
KW - SAT/satisfiability modulo theories (SMT) solver
KW - XOR (ARX) cipher
KW - automatic search
KW - lightweight block cipher
KW - rotation
UR - https://www.scopus.com/pages/publications/105005181834
U2 - 10.1109/JIOT.2025.3569746
DO - 10.1109/JIOT.2025.3569746
M3 - Article
AN - SCOPUS:105005181834
SN - 2327-4662
VL - 12
SP - 29989
EP - 30002
JO - IEEE Internet of Things Journal
JF - IEEE Internet of Things Journal
IS - 15
ER -