SCR-based ESD protection for high bandwidth DRAMs

Myounggon Kang; Ki Whan Song; Hoeju Chung; Jinyoung Kim; Yeong Taek Lee; Changhyun Kim

doi:10.1109/ASSCC.2007.4425767

SCR-based ESD protection for high bandwidth DRAMs

Myounggon Kang, Ki Whan Song, Hoeju Chung, Jinyoung Kim, Yeong Taek Lee, Changhyun Kim

School of Advanced Fusion Studies

Samsung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A modified SCR (silicon controlled rectifier) is proposed as an ESD protection for high speed signaling systems. With low voltage triggering (LVT) characteristics and good turn-on uniformity, the proposed SCR scheme accomplishes both goals, high discharging capability and C_in (input capacitance) reduction. The fabricated chips with the new ESD scheme passed the severe package level EOS test conditions such as HBM-5kV and MM-500V stress. The input capacitance, C_in, was measured to be 1.5pF which satisfies the DDR3-1066 specification with enough margin. We have observed in SPICE simulation that the data eye can be enlarged to 277ps (55.3% of UI) in DDR3 interface at 2Gbps operation due to the C_in reduction effect.

Original language	English
Title of host publication	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Pages	208-211
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2007.4425767
State	Published - 2007
Event	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of Duration: 12 Nov 2007 → 14 Nov 2007

Publication series

Name	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Conference

Conference	2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Country/Territory	Korea, Republic of
City	Jeju
Period	12/11/07 → 14/11/07

Keywords

DRAM
ESD
GGNMOS
High speed
Input capacitance
SCR

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10.1109/ASSCC.2007.4425767

Cite this

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title = "SCR-based ESD protection for high bandwidth DRAMs",

abstract = "A modified SCR (silicon controlled rectifier) is proposed as an ESD protection for high speed signaling systems. With low voltage triggering (LVT) characteristics and good turn-on uniformity, the proposed SCR scheme accomplishes both goals, high discharging capability and Cin (input capacitance) reduction. The fabricated chips with the new ESD scheme passed the severe package level EOS test conditions such as HBM-5kV and MM-500V stress. The input capacitance, Cin, was measured to be 1.5pF which satisfies the DDR3-1066 specification with enough margin. We have observed in SPICE simulation that the data eye can be enlarged to 277ps (55.3% of UI) in DDR3 interface at 2Gbps operation due to the Cin reduction effect.",

keywords = "DRAM, ESD, GGNMOS, High speed, Input capacitance, SCR",

author = "Myounggon Kang and Song, {Ki Whan} and Hoeju Chung and Jinyoung Kim and Lee, {Yeong Taek} and Changhyun Kim",

year = "2007",

doi = "10.1109/ASSCC.2007.4425767",

language = "English",

isbn = "1424413605",

series = "2007 IEEE Asian Solid-State Circuits Conference, A-SSCC",

pages = "208--211",

booktitle = "2007 IEEE Asian Solid-State Circuits Conference, A-SSCC",

note = "2007 IEEE Asian Solid-State Circuits Conference, A-SSCC ; Conference date: 12-11-2007 Through 14-11-2007",

}

Kang, M, Song, KW, Chung, H, Kim, J, Lee, YT & Kim, C 2007, SCR-based ESD protection for high bandwidth DRAMs. in 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC., 4425767, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, pp. 208-211, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, Jeju, Korea, Republic of, 12/11/07. https://doi.org/10.1109/ASSCC.2007.4425767

TY - GEN

T1 - SCR-based ESD protection for high bandwidth DRAMs

AU - Kang, Myounggon

AU - Song, Ki Whan

AU - Chung, Hoeju

AU - Kim, Jinyoung

AU - Lee, Yeong Taek

AU - Kim, Changhyun

PY - 2007

Y1 - 2007

N2 - A modified SCR (silicon controlled rectifier) is proposed as an ESD protection for high speed signaling systems. With low voltage triggering (LVT) characteristics and good turn-on uniformity, the proposed SCR scheme accomplishes both goals, high discharging capability and Cin (input capacitance) reduction. The fabricated chips with the new ESD scheme passed the severe package level EOS test conditions such as HBM-5kV and MM-500V stress. The input capacitance, Cin, was measured to be 1.5pF which satisfies the DDR3-1066 specification with enough margin. We have observed in SPICE simulation that the data eye can be enlarged to 277ps (55.3% of UI) in DDR3 interface at 2Gbps operation due to the Cin reduction effect.

AB - A modified SCR (silicon controlled rectifier) is proposed as an ESD protection for high speed signaling systems. With low voltage triggering (LVT) characteristics and good turn-on uniformity, the proposed SCR scheme accomplishes both goals, high discharging capability and Cin (input capacitance) reduction. The fabricated chips with the new ESD scheme passed the severe package level EOS test conditions such as HBM-5kV and MM-500V stress. The input capacitance, Cin, was measured to be 1.5pF which satisfies the DDR3-1066 specification with enough margin. We have observed in SPICE simulation that the data eye can be enlarged to 277ps (55.3% of UI) in DDR3 interface at 2Gbps operation due to the Cin reduction effect.

KW - DRAM

KW - ESD

KW - GGNMOS

KW - High speed

KW - Input capacitance

KW - SCR

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U2 - 10.1109/ASSCC.2007.4425767

DO - 10.1109/ASSCC.2007.4425767

M3 - Conference contribution

AN - SCOPUS:51349104397

SN - 1424413605

SN - 9781424413607

T3 - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

SP - 208

EP - 211

BT - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

T2 - 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Y2 - 12 November 2007 through 14 November 2007

ER -

SCR-based ESD protection for high bandwidth DRAMs

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Publication series

Conference

Keywords

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