Si single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic

Dae Hwan Kim; Suk Kang Sung; Kyung Rok Kim; Bum Ho Choi; Sung Woo Hwang; Doyeol Ahn; Jong Duk Lee; Byung Gook Park

doi:10.1109/IEDM.2001.979454

Si single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic

Dae Hwan Kim, Suk Kang Sung, Kyung Rok Kim, Bum Ho Choi, Sung Woo Hwang, Doyeol Ahn, Jong Duk Lee, Byung Gook Park

School of Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

9 Scopus citations

Abstract

Si single-electron transistors with sidewall depletion gates on a silicon-on-insulator nanowire are proposed and fabricated, using the combination of the conventional lithography and process technology. The size dependence of device characteristics shows good controllability and reproducibility, and a dynamic multi-functional SET logic is successfully demonstrated at 10 K, for the first time.

Original language	English
Pages (from-to)	151-154
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
DOIs	https://doi.org/10.1109/IEDM.2001.979454
State	Published - 2001

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title = "Si single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic",

abstract = "Si single-electron transistors with sidewall depletion gates on a silicon-on-insulator nanowire are proposed and fabricated, using the combination of the conventional lithography and process technology. The size dependence of device characteristics shows good controllability and reproducibility, and a dynamic multi-functional SET logic is successfully demonstrated at 10 K, for the first time.",

author = "Kim, {Dae Hwan} and Sung, {Suk Kang} and Kim, {Kyung Rok} and Choi, {Bum Ho} and Hwang, {Sung Woo} and Doyeol Ahn and Lee, {Jong Duk} and Park, {Byung Gook}",

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T1 - Si single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic

AU - Kim, Dae Hwan

AU - Sung, Suk Kang

AU - Kim, Kyung Rok

AU - Choi, Bum Ho

AU - Hwang, Sung Woo

AU - Ahn, Doyeol

AU - Lee, Jong Duk

AU - Park, Byung Gook

PY - 2001

Y1 - 2001

N2 - Si single-electron transistors with sidewall depletion gates on a silicon-on-insulator nanowire are proposed and fabricated, using the combination of the conventional lithography and process technology. The size dependence of device characteristics shows good controllability and reproducibility, and a dynamic multi-functional SET logic is successfully demonstrated at 10 K, for the first time.

AB - Si single-electron transistors with sidewall depletion gates on a silicon-on-insulator nanowire are proposed and fabricated, using the combination of the conventional lithography and process technology. The size dependence of device characteristics shows good controllability and reproducibility, and a dynamic multi-functional SET logic is successfully demonstrated at 10 K, for the first time.

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U2 - 10.1109/IEDM.2001.979454

DO - 10.1109/IEDM.2001.979454

M3 - Article

AN - SCOPUS:0035716655

SN - 0163-1918

SP - 151

EP - 154

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

ER -

Si single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic

Abstract

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