Silicon single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic

Dae Hwan Kim, Suk Kang Sung, Kyung Rok Kim, Jong Duk Lee, Byung Gook Park, Bum Ho Choi, Sung Woo Hwang, Doyeol Ahn

Research output: Contribution to journalArticlepeer-review

46 Scopus citations

Abstract

Novel single-electron transistors (SETs) with side-wall depletion gates on a silicon-on-insulator nanometer-scale wire are proposed and fabricated, using the combination of the conventional lithography and process technology. Clear Coulomb oscillation originated from the two electrically induced tunnel junctions and the single Si island between them is observed at 77 K. The island size dependence of the electrical characteristics shows the good controllability and reproducibility of the proposed fabrication method. Furthermore, the device characteristics are immune to gate bias conditions, and the position of Coulomb oscillation peak is controlled by the sidewall depletion gate voltage, without the additional gate electrode. Based on the current switching by sidewall gate voltage, the basic operation of the dynamic four-input multifunctional SET logic circuit is demonstrated at 10 K. The proposed SET offers the feasibility of the device design and optimization for SET logic circuits, in that its device parameters and circuit parameters are controllable by the conventional VLSI technology.

Original languageEnglish
Pages (from-to)627-635
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume49
Issue number4
DOIs
StatePublished - Apr 2002

Keywords

  • Controllability
  • Conventional lithography
  • Process technology
  • Reproducibility
  • SOI
  • Sidewall depletion gates

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