Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries

Jin Park, Sang Ho Lee, Ga Eon Kang, Jun Hyeok Heo, So Ra Jeon, Min Seok Kim, Seung Ji Bae, Jeong Woo Hong, Jae Won Jang, Jin Hyuk Bae, Sin Hyung Lee, In Man Kang

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM), based on polycrystalline silicon (poly-Si) nanotube structure with a grain boundary (GB), is designed and analyzed using technology computer-aided design (TCAD) simulation. In the proposed 1T-DRAM, the 1T-DRAM cell exhibited a sensing margin of 422 μA/μm and a retention time of 213 ms at T = 358 K with a single GB. To investigate the effect of random GBs, it was assumed that the number of GB is seven, and the memory characteristics depending on the location and number of GBs were analyzed. The memory performance rapidly degraded due to Shockley–Read–Hall recombination depending on the location and number of GBs. In the worst case, when the number of GB is 7, the mean of the sensing margin was 194 µA/µm, and the mean of the retention time was 50.4 ms. Compared to a single GB, the mean of the sensing margin and the retention time decreased by 59.7% and 77.4%, respectively.

Original languageEnglish
Article number2026
JournalNanomaterials
Volume13
Issue number13
DOIs
StatePublished - Jul 2023

Keywords

  • dual-gate
  • grain boundary
  • metal–oxide–semiconductor field-effect transistor
  • nanotube
  • one-transistor dynamic random-access memory
  • polycrystalline silicon
  • statistical analysis

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