Simulation of CMOS logic inverter based on vertically stacked polycrystalline silicon nanosheet gate-all-around MOSFET and its electrical characteristics

So Ra Min, Sang Ho Lee, Jin Park, Geon Uk Kim, Ga Eon Kang, Jun Hyeok Heo, Young Jun Yoon, Jae Hwa Seo, Jaewon Jang, Jin Hyuk Bae, Sin Hyung Lee, In Man Kang

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

The DC and inverter characteristics for the position of a single grain boundary (GB) in a nanosheet gate-all-around (GAA) MOSFET based on poly-crystalline silicon with three channels were analyzed. For the same channel layer, owing to the band banding by the drain voltage, the GB displays decreasing influence on the current as it moves towards the drain. The GB exhibits the highest on-state current of 6.89 × 10−4 A/μm when it is located at the drain. The DC characteristics determine the noise margin and delay time of the inverter. The higher the induced current, the lower the noise margin and delay time of the NMOS leading to improved characteristics of the inverter. The delay time when the GB existed in the drain, was considered to be the best in terms of DC performance as it was the lowest at 6.47 ps and showed 8.3% improvement in the switching characteristics.

Original languageEnglish
Pages (from-to)106-115
Number of pages10
JournalCurrent Applied Physics
Volume43
DOIs
StatePublished - Nov 2022

Keywords

  • CMOS inverter
  • Gate-all-around (GAA)
  • Grain boundary
  • Poly-Si
  • Vertically stacked nanosheet MOSFET

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