Simulation of CMOS logic inverter based on vertically stacked polycrystalline silicon nanosheet gate-all-around MOSFET and its electrical characteristics
- So Ra Min
- , Sang Ho Lee
- , Jin Park
- , Geon Uk Kim
- , Ga Eon Kang
- , Jun Hyeok Heo
- , Young Jun Yoon
- , Jae Hwa Seo
- , Jaewon Jang
- , Jin Hyuk Bae
- , Sin Hyung Lee
- , In Man Kang
- Kyungpook National University
- Korea Atomic Energy Research Institute
- Korea Electrotechnology Research Institute
Research output: Contribution to journal › Article › peer-review
5
Scopus
citations