Single chip implementation of MPEG-4 format conversion filters

This paper presents a single chip implementation of 6 format conversion filters proposed by MPEG. The chip uses only 59,000 transistors to provide functionality for 6 MPEG-4 FIR filters which require 85 coefficients and 16-bit internal precision. Two techniques have been used to implement the filters with extremely low cost. The first technique selects new filter coefficients for efficient VLSI implementation. By introducing the concept of efficient hardware implementation in an early stage of filter design, we could reduce hardware cost and design time considerably. The other technique is a new filter structure that provides functionality for 6 FIR filters with a single adder tree. The chip is the first known single chip implementation that provides functionality for MPEG-4 format conversion filters.