Single-crystalline Si STacked ARray (STAR) NAND flash memory

Jang Gn Yun; Garam Kim; Joung Eob Lee; Yoon Kim; Won Bo Shim; Jong Ho Lee; Hyungcheol Shin; Jong Duk Lee; Byung Gook Park

doi:10.1109/TED.2011.2107557

Single-crystalline Si STacked ARray (STAR) NAND flash memory

Jang Gn Yun, Garam Kim, Joung Eob Lee, Yoon Kim, Won Bo Shim, Jong Ho Lee, Hyungcheol Shin, Jong Duk Lee, Byung Gook Park

School of Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

32 Scopus citations

Abstract

In this paper, a 3-D nand Flash memory array having multiple single-crystal Si nanowires is investigated. Device structure and fabrication process are described including the electrical isolation of stacked nanowires. Numerical simulation results focused on nand Flash memory operation are delivered. Devices and array with stacked bit lines are fabricated, and memory characteristics such as program/erase select gate operation are measured. Array scheme is also discussed for the high-density bit-cost scalable 3-D stacked bit-line nand Flash memory application.

Original language	English
Article number	5729801
Pages (from-to)	1006-1014
Number of pages	9
Journal	IEEE Transactions on Electron Devices
Volume	58
Issue number	4
DOIs	https://doi.org/10.1109/TED.2011.2107557
State	Published - Apr 2011

Keywords

Damascene gate process
layer replacement and single-crystal Si nanowire
nand Flash memory
stacked bit lines
three-dimensional (3-D) memory

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10.1109/TED.2011.2107557

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title = "Single-crystalline Si STacked ARray (STAR) NAND flash memory",

abstract = "In this paper, a 3-D nand Flash memory array having multiple single-crystal Si nanowires is investigated. Device structure and fabrication process are described including the electrical isolation of stacked nanowires. Numerical simulation results focused on nand Flash memory operation are delivered. Devices and array with stacked bit lines are fabricated, and memory characteristics such as program/erase select gate operation are measured. Array scheme is also discussed for the high-density bit-cost scalable 3-D stacked bit-line nand Flash memory application.",

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author = "Yun, {Jang Gn} and Garam Kim and Lee, {Joung Eob} and Yoon Kim and Shim, {Won Bo} and Lee, {Jong Ho} and Hyungcheol Shin and Lee, {Jong Duk} and Park, {Byung Gook}",

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AU - Kim, Garam

AU - Lee, Joung Eob

AU - Kim, Yoon

AU - Shim, Won Bo

AU - Lee, Jong Ho

AU - Shin, Hyungcheol

AU - Lee, Jong Duk

AU - Park, Byung Gook

PY - 2011/4

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N2 - In this paper, a 3-D nand Flash memory array having multiple single-crystal Si nanowires is investigated. Device structure and fabrication process are described including the electrical isolation of stacked nanowires. Numerical simulation results focused on nand Flash memory operation are delivered. Devices and array with stacked bit lines are fabricated, and memory characteristics such as program/erase select gate operation are measured. Array scheme is also discussed for the high-density bit-cost scalable 3-D stacked bit-line nand Flash memory application.

AB - In this paper, a 3-D nand Flash memory array having multiple single-crystal Si nanowires is investigated. Device structure and fabrication process are described including the electrical isolation of stacked nanowires. Numerical simulation results focused on nand Flash memory operation are delivered. Devices and array with stacked bit lines are fabricated, and memory characteristics such as program/erase select gate operation are measured. Array scheme is also discussed for the high-density bit-cost scalable 3-D stacked bit-line nand Flash memory application.

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KW - layer replacement and single-crystal Si nanowire

KW - nand Flash memory

KW - stacked bit lines

KW - three-dimensional (3-D) memory

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Single-crystalline Si STacked ARray (STAR) NAND flash memory

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Keywords

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