Single electron transistors with sidewall depletion gates on a silicon-on-insulator quantum wire

D. H. Kim; K. R. Kim; S. K. Sung; B. H. Choi; S. W. Hwang; D. Ahn; J. D. Lee; B. G. Park

Single electron transistors with sidewall depletion gates on a silicon-on-insulator quantum wire

D. H. Kim, K. R. Kim, S. K. Sung, B. H. Choi, S. W. Hwang, D. Ahn, J. D. Lee, B. G. Park

School of Electrical and Computer Engineering

Seoul National University

Research output: Contribution to conference › Paper › peer-review

2 Scopus citations

Abstract

The fabrication of single electron transistors (SET) with sidewall depletion gates on a silicon on insulator (SOI) quantum wire was proposed. A combination of conventional lithography and VLSI technology was used for the fabrication. The charge of electrically formed quantum dots was controlled by the control gate bias. The separation between the two sidewall gates was designed to be 37 nm and 185 nm respectively for the two SETs to incorporate high temperature operation and high voltage gain. The three-dimensional device simulation confirmed reliable operation of the Si based SET at 77K.

Original language	English
Pages	133-134
Number of pages	2
State	Published - 2001
Event	Device Research Conference (DRC) - Notre Dame, IN, United States Duration: 25 Jun 2001 → 27 Jun 2001

Conference

Conference	Device Research Conference (DRC)
Country/Territory	United States
City	Notre Dame, IN
Period	25/06/01 → 27/06/01

Cite this

@conference{a1c2d8843b2348709db9d1fc957b6673,

title = "Single electron transistors with sidewall depletion gates on a silicon-on-insulator quantum wire",

abstract = "The fabrication of single electron transistors (SET) with sidewall depletion gates on a silicon on insulator (SOI) quantum wire was proposed. A combination of conventional lithography and VLSI technology was used for the fabrication. The charge of electrically formed quantum dots was controlled by the control gate bias. The separation between the two sidewall gates was designed to be 37 nm and 185 nm respectively for the two SETs to incorporate high temperature operation and high voltage gain. The three-dimensional device simulation confirmed reliable operation of the Si based SET at 77K.",

author = "Kim, {D. H.} and Kim, {K. R.} and Sung, {S. K.} and Choi, {B. H.} and Hwang, {S. W.} and D. Ahn and Lee, {J. D.} and Park, {B. G.}",

year = "2001",

language = "English",

pages = "133--134",

note = "Device Research Conference (DRC) ; Conference date: 25-06-2001 Through 27-06-2001",

}

TY - CONF

T1 - Single electron transistors with sidewall depletion gates on a silicon-on-insulator quantum wire

AU - Kim, D. H.

AU - Kim, K. R.

AU - Sung, S. K.

AU - Choi, B. H.

AU - Hwang, S. W.

AU - Ahn, D.

AU - Lee, J. D.

AU - Park, B. G.

PY - 2001

Y1 - 2001

N2 - The fabrication of single electron transistors (SET) with sidewall depletion gates on a silicon on insulator (SOI) quantum wire was proposed. A combination of conventional lithography and VLSI technology was used for the fabrication. The charge of electrically formed quantum dots was controlled by the control gate bias. The separation between the two sidewall gates was designed to be 37 nm and 185 nm respectively for the two SETs to incorporate high temperature operation and high voltage gain. The three-dimensional device simulation confirmed reliable operation of the Si based SET at 77K.

AB - The fabrication of single electron transistors (SET) with sidewall depletion gates on a silicon on insulator (SOI) quantum wire was proposed. A combination of conventional lithography and VLSI technology was used for the fabrication. The charge of electrically formed quantum dots was controlled by the control gate bias. The separation between the two sidewall gates was designed to be 37 nm and 185 nm respectively for the two SETs to incorporate high temperature operation and high voltage gain. The three-dimensional device simulation confirmed reliable operation of the Si based SET at 77K.

UR - http://www.scopus.com/inward/record.url?scp=0034875655&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0034875655

SP - 133

EP - 134

T2 - Device Research Conference (DRC)

Y2 - 25 June 2001 through 27 June 2001

ER -

Single electron transistors with sidewall depletion gates on a silicon-on-insulator quantum wire

Abstract

Conference

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