Small size low noise amplifier with suppressed noise from gate resistance

Ickhyun Song, Hee Sauk Jhon, Hakchul Jung, Minsuk Koo, Hyungcheol Shin

Research output: Contribution to journalArticlepeer-review

Abstract

In this article, design and characterization results of a fully integrated 5.8 GHz low noise amplifier (LNA) using 0.13-μm CMOS technology are presented. Commonly adopted inductive source degeneration for input impedance matching is eliminated to achieve smaller chip area while providing reasonable 50-Ω matching. Also by adding a capacitor between the gate and the source of the input transistor, a noise source from the gate resistance is partly suppressed. The layout of the designed LNA occupies total area of 0.68 mm 2 and the results show forward power gain (S21) of 12.7 dB and noise figure of 3.9 dB while consuming 6.85 mW from 1.2-V DC supply.

Original languageEnglish
Pages (from-to)2300-2304
Number of pages5
JournalMicrowave and Optical Technology Letters
Volume50
Issue number9
DOIs
StatePublished - Sep 2008

Keywords

  • CMOS
  • Gate resistance
  • Impedance matching
  • Low noise amplifier (LNA)
  • Noise

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