Solution-processed charge-trap/ferroelectric hybrid memory transistor for enhanced data storage and neuromorphic computing

The demand for highly integrated memory and neuromorphic computing systems in flexible, large-area electronics has spurred interest in solution-processed, high-density memory components. However, achieving reliable multi-level memory states with high current ratios remains a challenge for solution-based memory devices. Here, we report dual-gate multi-bit memory transistors that combine charge-trap and ferroelectric effects. Using a chemically stable oxide semiconductor, we fabricate stacked charge-trap and ferroelectric films without solvent orthogonality issues. These devices exhibit reliable non-volatile memory states with high current ratios (>10), enabling practical applications in memory and computing systems. A NAND flash memory system based on these transistors demonstrates stable operation and high integration density, accommodating 20 distinct cells per word line. Furthermore, these memory transistors serve as artificial synapses with the high dynamic range (∼181), providing stable synaptic weights analogous to biological counterparts. This approach establishes a versatile platform for solution-processed multi-bit memory and neuromorphic electronics.