Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process

Giyoung Yang; Hakchul Jung; Jinyoung Lim; Jaewoo Seo; Ingyum Kim; Jisu Yu; Hyeoungyu You; Jeongsoon Kong; Garoom Kim; Minjae Jeong; Chanhee Park; Sera An; Woojin Rim; Hayoung Kim; Dalhee Lee; Sanghoon Baek; Jonghoon Jung; Taejoong Song; Jongwook Kye

doi:10.1109/VLSITechnologyandCir46769.2022.9830450

Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process

Giyoung Yang, Hakchul Jung, Jinyoung Lim, Jaewoo Seo, Ingyum Kim, Jisu Yu, Hyeoungyu You, Jeongsoon Kong, Garoom Kim, Minjae Jeong, Chanhee Park, Sera An, Woojin Rim, Hayoung Kim, Dalhee Lee, Sanghoon Baek, Jonghoon Jung, Taejoong Song, Jongwook Kye

Department of Mechanical and Information Engineering

Samsung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In this paper, standard cell design challenges for the 3nm process are introduced, solved, and optimized using the advanced MOL technology, AC P-N connection. In this methodology, each drain nodes of P and NMOS are connected using a single MOL layer (AC). Utilizing the AC P-N connection, standard cell library can be improved in three different ways. First, reduce the parasitic wire resistance by more than 20% and improve circuit reliability by alleviating a high current density. Second, Ceff improvement by composing only the MOL layer (AC) for the output node of the cell improves the standard cell speed up to 9.6%. Third, we propose a novel Flip-Flop (FF) structure optimized for AC P-N connection, thus improving the speed of the FF (1/TD2Q) by 9.1%.

Original language	English
Title of host publication	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	363-364
Number of pages	2
ISBN (Electronic)	9781665497725
DOIs	https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830450
State	Published - 2022
Event	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States Duration: 12 Jun 2022 → 17 Jun 2022

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2022-June
ISSN (Print)	0743-1562

Conference

Conference	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/Territory	United States
City	Honolulu
Period	12/06/22 → 17/06/22

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10.1109/VLSITechnologyandCir46769.2022.9830450

Cite this

Yang, G., Jung, H., Lim, J., Seo, J., Kim, I., Yu, J., You, H., Kong, J., Kim, G., Jeong, M., Park, C., An, S., Rim, W., Kim, H., Lee, D., Baek, S., Jung, J., Song, T., & Kye, J. (2022). Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 (pp. 363-364). (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830450

@inproceedings{8a953ad0e6814b36be1309f74e495e0d,

title = "Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process",

abstract = "In this paper, standard cell design challenges for the 3nm process are introduced, solved, and optimized using the advanced MOL technology, AC P-N connection. In this methodology, each drain nodes of P and NMOS are connected using a single MOL layer (AC). Utilizing the AC P-N connection, standard cell library can be improved in three different ways. First, reduce the parasitic wire resistance by more than 20% and improve circuit reliability by alleviating a high current density. Second, Ceff improvement by composing only the MOL layer (AC) for the output node of the cell improves the standard cell speed up to 9.6%. Third, we propose a novel Flip-Flop (FF) structure optimized for AC P-N connection, thus improving the speed of the FF (1/TD2Q) by 9.1%.",

author = "Giyoung Yang and Hakchul Jung and Jinyoung Lim and Jaewoo Seo and Ingyum Kim and Jisu Yu and Hyeoungyu You and Jeongsoon Kong and Garoom Kim and Minjae Jeong and Chanhee Park and Sera An and Woojin Rim and Hayoung Kim and Dalhee Lee and Sanghoon Baek and Jonghoon Jung and Taejoong Song and Jongwook Kye",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 ; Conference date: 12-06-2022 Through 17-06-2022",

year = "2022",

doi = "10.1109/VLSITechnologyandCir46769.2022.9830450",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "363--364",

booktitle = "2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022",

address = "United States",

}

Yang, G, Jung, H, Lim, J, Seo, J, Kim, I, Yu, J, You, H, Kong, J, Kim, G, Jeong, M, Park, C, An, S, Rim, W, Kim, H, Lee, D, Baek, S, Jung, J, Song, T & Kye, J 2022, Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process. in 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2022-June, Institute of Electrical and Electronics Engineers Inc., pp. 363-364, 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022, Honolulu, United States, 12/06/22. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830450

Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process. / Yang, Giyoung; Jung, Hakchul; Lim, Jinyoung et al.
2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 363-364 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process

AU - Yang, Giyoung

AU - Jung, Hakchul

AU - Lim, Jinyoung

AU - Seo, Jaewoo

AU - Kim, Ingyum

AU - Yu, Jisu

AU - You, Hyeoungyu

AU - Kong, Jeongsoon

AU - Kim, Garoom

AU - Jeong, Minjae

AU - Park, Chanhee

AU - An, Sera

AU - Rim, Woojin

AU - Kim, Hayoung

AU - Lee, Dalhee

AU - Baek, Sanghoon

AU - Jung, Jonghoon

AU - Song, Taejoong

AU - Kye, Jongwook

PY - 2022

Y1 - 2022

N2 - In this paper, standard cell design challenges for the 3nm process are introduced, solved, and optimized using the advanced MOL technology, AC P-N connection. In this methodology, each drain nodes of P and NMOS are connected using a single MOL layer (AC). Utilizing the AC P-N connection, standard cell library can be improved in three different ways. First, reduce the parasitic wire resistance by more than 20% and improve circuit reliability by alleviating a high current density. Second, Ceff improvement by composing only the MOL layer (AC) for the output node of the cell improves the standard cell speed up to 9.6%. Third, we propose a novel Flip-Flop (FF) structure optimized for AC P-N connection, thus improving the speed of the FF (1/TD2Q) by 9.1%.

AB - In this paper, standard cell design challenges for the 3nm process are introduced, solved, and optimized using the advanced MOL technology, AC P-N connection. In this methodology, each drain nodes of P and NMOS are connected using a single MOL layer (AC). Utilizing the AC P-N connection, standard cell library can be improved in three different ways. First, reduce the parasitic wire resistance by more than 20% and improve circuit reliability by alleviating a high current density. Second, Ceff improvement by composing only the MOL layer (AC) for the output node of the cell improves the standard cell speed up to 9.6%. Third, we propose a novel Flip-Flop (FF) structure optimized for AC P-N connection, thus improving the speed of the FF (1/TD2Q) by 9.1%.

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U2 - 10.1109/VLSITechnologyandCir46769.2022.9830450

DO - 10.1109/VLSITechnologyandCir46769.2022.9830450

M3 - Conference contribution

AN - SCOPUS:85135207937

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 363

EP - 364

BT - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022

Y2 - 12 June 2022 through 17 June 2022

ER -

Yang G, Jung H, Lim J, Seo J, Kim I, Yu J et al. Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 363-364. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSITechnologyandCir46769.2022.9830450

Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process

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