TY - GEN
T1 - Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process
AU - Yang, Giyoung
AU - Jung, Hakchul
AU - Lim, Jinyoung
AU - Seo, Jaewoo
AU - Kim, Ingyum
AU - Yu, Jisu
AU - You, Hyeoungyu
AU - Kong, Jeongsoon
AU - Kim, Garoom
AU - Jeong, Minjae
AU - Park, Chanhee
AU - An, Sera
AU - Rim, Woojin
AU - Kim, Hayoung
AU - Lee, Dalhee
AU - Baek, Sanghoon
AU - Jung, Jonghoon
AU - Song, Taejoong
AU - Kye, Jongwook
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - In this paper, standard cell design challenges for the 3nm process are introduced, solved, and optimized using the advanced MOL technology, AC P-N connection. In this methodology, each drain nodes of P and NMOS are connected using a single MOL layer (AC). Utilizing the AC P-N connection, standard cell library can be improved in three different ways. First, reduce the parasitic wire resistance by more than 20% and improve circuit reliability by alleviating a high current density. Second, Ceff improvement by composing only the MOL layer (AC) for the output node of the cell improves the standard cell speed up to 9.6%. Third, we propose a novel Flip-Flop (FF) structure optimized for AC P-N connection, thus improving the speed of the FF (1/TD2Q) by 9.1%.
AB - In this paper, standard cell design challenges for the 3nm process are introduced, solved, and optimized using the advanced MOL technology, AC P-N connection. In this methodology, each drain nodes of P and NMOS are connected using a single MOL layer (AC). Utilizing the AC P-N connection, standard cell library can be improved in three different ways. First, reduce the parasitic wire resistance by more than 20% and improve circuit reliability by alleviating a high current density. Second, Ceff improvement by composing only the MOL layer (AC) for the output node of the cell improves the standard cell speed up to 9.6%. Third, we propose a novel Flip-Flop (FF) structure optimized for AC P-N connection, thus improving the speed of the FF (1/TD2Q) by 9.1%.
UR - https://www.scopus.com/pages/publications/85135207937
U2 - 10.1109/VLSITechnologyandCir46769.2022.9830450
DO - 10.1109/VLSITechnologyandCir46769.2022.9830450
M3 - Conference contribution
AN - SCOPUS:85135207937
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 363
EP - 364
BT - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Y2 - 12 June 2022 through 17 June 2022
ER -