Structural and electrical properties of ferroelectric-gate field-effect-transistors using Au/(Bi,La)4Ti3O 12/SrTa2O6/Si structures

Ho Seung Jeon, Jeong Hwan Kim, Joo Nam Kim, Kwang Hun Park, Byung Eun Park

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

We fabricated the ferroelectric-gate field effect transistors (Fe-FETs) using a metal-ferroelectric-insulator-semiconductor (MFIS) structure as a gate configuration using (Bi,La)4Ti3O12 (BLT) and SrTa2O6 (STA) thin films. From the capacitance-voltage (C-V) measurements for MFIS capacitors, a hysteric shift with a clockwise direction was observed and the memory window width was about 1.5 V for the ±5 V bias sweep. The leakage current density was as low as 1×10-7 A/cm2 at 5 V. From drain current-gate voltage characteristics of the fabricated Fe-FETs, the obtained threshold voltage shift (memory window) of the device was about 0.5 V due to the ferroelectric nature of BLT film. The drain current-drain voltage characteristics of the fabricated Fe-FETs showed typical n-channel FETs characteristics.

Original languageEnglish
Title of host publication2007 16th IEEE International Symposium on the Applications of Ferroelectrics, ISAF
Pages65-68
Number of pages4
DOIs
StatePublished - 2007
Event2007 16th IEEE International Symposium on the Applications of Ferroelectrics, ISAF - Nara-city, Japan
Duration: 27 May 200731 May 2007

Publication series

NameIEEE International Symposium on Applications of Ferroelectrics

Conference

Conference2007 16th IEEE International Symposium on the Applications of Ferroelectrics, ISAF
Country/TerritoryJapan
CityNara-city
Period27/05/0731/05/07

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