Testing of programmable analog neural network processors

S. M. Gowda; Bing J. Sheu; Joongho Choi

doi:10.1109/CICC.1992.591324

Testing of programmable analog neural network processors

S. M. Gowda, Bing J. Sheu, Joongho Choi

School of Electrical and Computer Engineering

University of Southern California

Research output: Contribution to journal › Conference article › peer-review

1 Scopus citations

Abstract

Artificial neural networks are capable of high-speed computation to solve many complex problems in scientific and engineering applications. A systematic method to test large arrays of analog, digital, or mixed-signal circuit components that constitute these networks is described. The testing procedure consists of a parametric test and a behavioral test. Characteristics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Several measurement results from neural network chips are presented to demonstrate the testing procedure.

Original language	English
Article number	5727372
Pages (from-to)	17.1.1-17.1.4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.1992.591324
State	Published - 1992
Event	14th Annual Custom Integrated Circuits Conference, CICC 1992 - Boston, MA, United States Duration: 3 May 1992 → 6 May 1992

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title = "Testing of programmable analog neural network processors",

abstract = "Artificial neural networks are capable of high-speed computation to solve many complex problems in scientific and engineering applications. A systematic method to test large arrays of analog, digital, or mixed-signal circuit components that constitute these networks is described. The testing procedure consists of a parametric test and a behavioral test. Characteristics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Several measurement results from neural network chips are presented to demonstrate the testing procedure.",

author = "Gowda, {S. M.} and Sheu, {Bing J.} and Joongho Choi",

year = "1992",

doi = "10.1109/CICC.1992.591324",

language = "English",

pages = "17.1.1--17.1.4",

journal = "Proceedings of the Custom Integrated Circuits Conference",

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note = "14th Annual Custom Integrated Circuits Conference, CICC 1992 ; Conference date: 03-05-1992 Through 06-05-1992",

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AU - Choi, Joongho

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AB - Artificial neural networks are capable of high-speed computation to solve many complex problems in scientific and engineering applications. A systematic method to test large arrays of analog, digital, or mixed-signal circuit components that constitute these networks is described. The testing procedure consists of a parametric test and a behavioral test. Characteristics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Several measurement results from neural network chips are presented to demonstrate the testing procedure.

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DO - 10.1109/CICC.1992.591324

M3 - Conference article

AN - SCOPUS:84869997934

SN - 0886-5930

SP - 17.1.1-17.1.4

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T2 - 14th Annual Custom Integrated Circuits Conference, CICC 1992

Y2 - 3 May 1992 through 6 May 1992

ER -

Testing of programmable analog neural network processors

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