The Optimization of Program Operation for Low Power Consumption in 3D Ferroelectric (Fe)-NAND Flash Memory

This paper proposes an optimized program operation method for ferroelectric NAND (FE-NAND) flash memory utilizing the gate-induced drain leakage (GIDL) program and validated through simulations. The program operation was performed by setting the time for the unselected cell to reach the pass voltage (V_pass) to 0.1 µs, 0.2 µs, and 0.3 µs, respectively. As the time for the unselected word line (WL) to reach V_pass increases, the channel potential increases due to a decrease in the electron–hole recombination rate. After the program operation, the threshold voltage (V_th) shift of the selected cell and the pass disturb of the unselected cells according to the V_pass condition were analyzed. Consequently, there was a more significant change in V_th among selected cells compared to the time for unselected cells to reach V_pass as 0.1 µs. The findings of this study suggest an optimal program operation that increases slowly and decreases rapidly through the variation of V_th according to the program operation. By performing the proposed program operation, we confirmed that low-power operation is achievable by reducing the WL voltage by 2 V and the bit line (BL) voltage by 1 V, in contrast to the conventional GIDL program.