The study of relation between variable retention time and channel implantation

In this paper, we investigate a Random Telegraph Signal (RTS) like junction leakage current causing a variable retention time (VRT) problem in Dynamic Random Access Memory (DRAM) cells. With sample devices which have different channel doping concentration, hold times of high leakage state and low leakage state are extracted in diverse storage node bias conditions, and their ratios are analyzed based on a simple equation. The hold time ratio of two states decreases with the increasing bias in high channel doping samples, while it increases in both regular channel doping samples and low channel doping samples.