Three-dimensional and flash memory

Y. Kim, I. H. Park, H. T. Kwon, D. Wee, B. G. Park

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

High-density and high-speed charge-trapping AND flash memory array is fabricated for the first time. A reliability of 104 endurance cycles and uniform program/erase characteristics along with a threshold voltage window >3 V is obtained. The AND array has several advantages, such as high read current drivability regardless of the number of word-lines, immunity to back-pattern dependency, and fast bit-sensing speed based on a parallel connected cell array structure, which are highly appropriate for three-dimensional (3D) stacking. Finally, a novel 3D stacked vertical-AND array is proposed to surpass the limitations of the conventional 3D NAND flash memories.

Original languageEnglish
Pages (from-to)739-741
Number of pages3
JournalElectronics Letters
Volume53
Issue number11
DOIs
StatePublished - 25 May 2017

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