Three-dimensional and flash memory

Y. Kim; I. H. Park; H. T. Kwon; D. Wee; B. G. Park

doi:10.1049/el.2017.0465

Three-dimensional and flash memory

Y. Kim, I. H. Park, H. T. Kwon, D. Wee, B. G. Park

School of Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

High-density and high-speed charge-trapping AND flash memory array is fabricated for the first time. A reliability of 10⁴ endurance cycles and uniform program/erase characteristics along with a threshold voltage window >3 V is obtained. The AND array has several advantages, such as high read current drivability regardless of the number of word-lines, immunity to back-pattern dependency, and fast bit-sensing speed based on a parallel connected cell array structure, which are highly appropriate for three-dimensional (3D) stacking. Finally, a novel 3D stacked vertical-AND array is proposed to surpass the limitations of the conventional 3D NAND flash memories.

Original language	English
Pages (from-to)	739-741
Number of pages	3
Journal	Electronics Letters
Volume	53
Issue number	11
DOIs	https://doi.org/10.1049/el.2017.0465
State	Published - 25 May 2017

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title = "Three-dimensional and flash memory",

abstract = "High-density and high-speed charge-trapping AND flash memory array is fabricated for the first time. A reliability of 104 endurance cycles and uniform program/erase characteristics along with a threshold voltage window >3 V is obtained. The AND array has several advantages, such as high read current drivability regardless of the number of word-lines, immunity to back-pattern dependency, and fast bit-sensing speed based on a parallel connected cell array structure, which are highly appropriate for three-dimensional (3D) stacking. Finally, a novel 3D stacked vertical-AND array is proposed to surpass the limitations of the conventional 3D NAND flash memories.",

author = "Y. Kim and Park, \{I. H.\} and Kwon, \{H. T.\} and D. Wee and Park, \{B. G.\}",

note = "Publisher Copyright: {\textcopyright} The Institution of Engineering and Technology 2017.",

year = "2017",

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doi = "10.1049/el.2017.0465",

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journal = "Electronics Letters",

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T1 - Three-dimensional and flash memory

AU - Kim, Y.

AU - Park, I. H.

AU - Kwon, H. T.

AU - Wee, D.

AU - Park, B. G.

PY - 2017/5/25

Y1 - 2017/5/25

N2 - High-density and high-speed charge-trapping AND flash memory array is fabricated for the first time. A reliability of 104 endurance cycles and uniform program/erase characteristics along with a threshold voltage window >3 V is obtained. The AND array has several advantages, such as high read current drivability regardless of the number of word-lines, immunity to back-pattern dependency, and fast bit-sensing speed based on a parallel connected cell array structure, which are highly appropriate for three-dimensional (3D) stacking. Finally, a novel 3D stacked vertical-AND array is proposed to surpass the limitations of the conventional 3D NAND flash memories.

AB - High-density and high-speed charge-trapping AND flash memory array is fabricated for the first time. A reliability of 104 endurance cycles and uniform program/erase characteristics along with a threshold voltage window >3 V is obtained. The AND array has several advantages, such as high read current drivability regardless of the number of word-lines, immunity to back-pattern dependency, and fast bit-sensing speed based on a parallel connected cell array structure, which are highly appropriate for three-dimensional (3D) stacking. Finally, a novel 3D stacked vertical-AND array is proposed to surpass the limitations of the conventional 3D NAND flash memories.

UR - https://www.scopus.com/pages/publications/85019715745

U2 - 10.1049/el.2017.0465

DO - 10.1049/el.2017.0465

M3 - Article

AN - SCOPUS:85019715745

SN - 0013-5194

VL - 53

SP - 739

EP - 741

JO - Electronics Letters

JF - Electronics Letters

IS - 11

ER -

Three-dimensional and flash memory

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