TY - JOUR

T1 - Transient modelling of single-electron transistors for efficient circuit simulation by SPICE

AU - Yu, Y. S.

AU - Hwang, S. W.

AU - Ahn, D.

PY - 2005/12

Y1 - 2005/12

N2 - In the paper, a regime, where the independent treatment of single-electron transistors (SETs) in transient simulations is valid, has been identified quantitatively. It is found that, as in the steady-state case, although the temperature varies, each SET can be treated independently, even in the transient case when the interconnection capacitance is large enough. However, the value of the load capacitance CL of the interconnections for the independent treatment of SETs is approximately ten times larger than that of the steady-state case. A compact SET transient model is developed for transient circuit simulation by SPICE. The developed model is based on a linearised equivalent circuit and the solution of a master equation is done by the programming capabilities of the SmartSpice. Exact delineation of several simulation time scales and the physics-based compact model make it possible to accurately simulate hybrid circuits in the timescales down to several tens of picoseconds.

AB - In the paper, a regime, where the independent treatment of single-electron transistors (SETs) in transient simulations is valid, has been identified quantitatively. It is found that, as in the steady-state case, although the temperature varies, each SET can be treated independently, even in the transient case when the interconnection capacitance is large enough. However, the value of the load capacitance CL of the interconnections for the independent treatment of SETs is approximately ten times larger than that of the steady-state case. A compact SET transient model is developed for transient circuit simulation by SPICE. The developed model is based on a linearised equivalent circuit and the solution of a master equation is done by the programming capabilities of the SmartSpice. Exact delineation of several simulation time scales and the physics-based compact model make it possible to accurately simulate hybrid circuits in the timescales down to several tens of picoseconds.

UR - http://www.scopus.com/inward/record.url?scp=29144471157&partnerID=8YFLogxK

U2 - 10.1049/ip-cds:20045107

DO - 10.1049/ip-cds:20045107

M3 - Article

AN - SCOPUS:29144471157

SN - 1350-2409

VL - 152

SP - 691

EP - 696

JO - IEE Proceedings: Circuits, Devices and Systems

JF - IEE Proceedings: Circuits, Devices and Systems

IS - 6

ER -