Various extraction methods for parasitic capacitances in nanowire FET

In this paper, we proposed various methods to extract parasitic capacitance components for nanowire FET using a 3D Technology computer-aided design (TCAD) simulation. First, parasitic capacitance components were extracted by ideal method using the structure without spacer. The extracted results and calculated values were almost identical. Next, non-ideal methods with varying spacer length and dielectric constant of spacer were used to extract parasitic capacitance components. The method using spacer length accompanies structural change that relatively large error occurred when extracting outer fringing capacitances. However, the method with varying dielectric constant of spacer does not has any structural change. This method showed much smaller error than the method with varying spacer length. Also, it was found to show almost same results extracted by the ideal method.