Vertical channel double split-gate (VCDSG) flash memory

Jang Gn Yun; Il Han Park; Jung Hoon Lee; Se Hwan Park; Yoon Kim; Dong Hua Lee; Seongjae Cho; Doo Hyun Kim; Gil Sung Lee; Won Bo Sim; Jong Duk Lee; Byung Gook Park

doi:10.1109/SNW.2008.5418393

School of Electrical and Computer Engineering

Seoul National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A novel vertical channel double split-gate (VCDSG) flash memory is investigated. As well as the single-level operation, this device is especially useful for the multi-level cell (MLC) to operate as a 4-bit/cell. Operation and fabrication issues related with the 3-dimensional cell structure are addressed. For high density integration, simple contact array scheme is proposed.

Original language	English
Title of host publication	IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
DOIs	https://doi.org/10.1109/SNW.2008.5418393
State	Published - 2008
Event	IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 - Honolulu, HI, United States Duration: 15 Jun 2008 → 16 Jun 2008

Publication series

Name	IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

Conference

Conference	IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008
Country/Territory	United States
City	Honolulu, HI
Period	15/06/08 → 16/06/08

Access to Document

10.1109/SNW.2008.5418393

Cite this

Yun, J. G., Park, I. H., Lee, J. H., Park, S. H., Kim, Y., Lee, D. H., Cho, S., Kim, D. H., Lee, G. S., Sim, W. B., Lee, J. D., & Park, B. G. (2008). Vertical channel double split-gate (VCDSG) flash memory. In IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 Article 5418393 (IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008). https://doi.org/10.1109/SNW.2008.5418393

@inproceedings{601810bb8b9b4952a078aff00c7a3908,

title = "Vertical channel double split-gate (VCDSG) flash memory",

abstract = "A novel vertical channel double split-gate (VCDSG) flash memory is investigated. As well as the single-level operation, this device is especially useful for the multi-level cell (MLC) to operate as a 4-bit/cell. Operation and fabrication issues related with the 3-dimensional cell structure are addressed. For high density integration, simple contact array scheme is proposed.",

author = "Yun, \{Jang Gn\} and Park, \{Il Han\} and Lee, \{Jung Hoon\} and Park, \{Se Hwan\} and Yoon Kim and Lee, \{Dong Hua\} and Seongjae Cho and Kim, \{Doo Hyun\} and Lee, \{Gil Sung\} and Sim, \{Won Bo\} and Lee, \{Jong Duk\} and Park, \{Byung Gook\}",

year = "2008",

doi = "10.1109/SNW.2008.5418393",

language = "English",

isbn = "9781424420711",

series = "IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008",

booktitle = "IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008",

note = "IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008 ; Conference date: 15-06-2008 Through 16-06-2008",

}

Yun, JG, Park, IH, Lee, JH, Park, SH, Kim, Y, Lee, DH, Cho, S, Kim, DH, Lee, GS, Sim, WB, Lee, JD & Park, BG 2008, Vertical channel double split-gate (VCDSG) flash memory. in IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008., 5418393, IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008, IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008, Honolulu, HI, United States, 15/06/08. https://doi.org/10.1109/SNW.2008.5418393

TY - GEN

T1 - Vertical channel double split-gate (VCDSG) flash memory

AU - Yun, Jang Gn

AU - Park, Il Han

AU - Lee, Jung Hoon

AU - Park, Se Hwan

AU - Kim, Yoon

AU - Lee, Dong Hua

AU - Cho, Seongjae

AU - Kim, Doo Hyun

AU - Lee, Gil Sung

AU - Sim, Won Bo

AU - Lee, Jong Duk

AU - Park, Byung Gook

PY - 2008

Y1 - 2008

N2 - A novel vertical channel double split-gate (VCDSG) flash memory is investigated. As well as the single-level operation, this device is especially useful for the multi-level cell (MLC) to operate as a 4-bit/cell. Operation and fabrication issues related with the 3-dimensional cell structure are addressed. For high density integration, simple contact array scheme is proposed.

AB - A novel vertical channel double split-gate (VCDSG) flash memory is investigated. As well as the single-level operation, this device is especially useful for the multi-level cell (MLC) to operate as a 4-bit/cell. Operation and fabrication issues related with the 3-dimensional cell structure are addressed. For high density integration, simple contact array scheme is proposed.

UR - https://www.scopus.com/pages/publications/77949949578

U2 - 10.1109/SNW.2008.5418393

DO - 10.1109/SNW.2008.5418393

M3 - Conference contribution

AN - SCOPUS:77949949578

SN - 9781424420711

T3 - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

BT - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

T2 - IEEE 2008 Silicon Nanoelectronics Workshop, SNW 2008

Y2 - 15 June 2008 through 16 June 2008

ER -