TY - GEN
T1 - Vertical-channel stacked array (VCSTAR) for 3D NAND flash memory
AU - Kim, Yoon
AU - Park, Se Hwan
AU - Kim, Wandong
AU - Seo, Joo Yon
AU - Park, Byung Gook
PY - 2011
Y1 - 2011
N2 - Recently, 3D stacked NAND flash architectures have been proposed to solve scaling limit of the planar NAND flash memory based on floating-gate type [1]-[2]. However, theses structures have several drawbacks. For TCAT[1], declined hole-etch slope leads to different curvature radius of each stacked active layers. Consequently, different elecric field is applied to each layer in program operation, which causes the threshold voltage distribution problem. In case of VSAT[2], it is almost impossible to implement metal gate structure. Also, VSAT has the limitation of the stacking extendability due to inefficient bit line current flow (going up and down).
AB - Recently, 3D stacked NAND flash architectures have been proposed to solve scaling limit of the planar NAND flash memory based on floating-gate type [1]-[2]. However, theses structures have several drawbacks. For TCAT[1], declined hole-etch slope leads to different curvature radius of each stacked active layers. Consequently, different elecric field is applied to each layer in program operation, which causes the threshold voltage distribution problem. In case of VSAT[2], it is almost impossible to implement metal gate structure. Also, VSAT has the limitation of the stacking extendability due to inefficient bit line current flow (going up and down).
UR - http://www.scopus.com/inward/record.url?scp=84863127196&partnerID=8YFLogxK
U2 - 10.1109/ISDRS.2011.6135406
DO - 10.1109/ISDRS.2011.6135406
M3 - Conference contribution
AN - SCOPUS:84863127196
SN - 9781457717550
T3 - 2011 International Semiconductor Device Research Symposium, ISDRS 2011
BT - 2011 International Semiconductor Device Research Symposium, ISDRS 2011
T2 - 2011 International Semiconductor Device Research Symposium, ISDRS 2011
Y2 - 7 December 2011 through 9 December 2011
ER -