VLSI Design of Compact and High-Precision Analog Neural Network Processors

Design and nieasurement of an analog VLSI neural network processor for scientific and engineering applications such as pattern recognition and image compression are described. The backpropagation and self-organization learning schemes in artificial neural networks require the high-precision multiplication and summation. The analog neural network design ja-esented in this paper performs high-speed feedforward computatiœi in parallel. A digital signal processor or a host computer can be used for updating of synapse weights during the learning phase. The analog computing blocks consist of a synapse matrix and the input and oatpat neuron arrays. The output neuron is composed of a current-to-voltage converter and a sigmoid function generator with a controllable voltage gain. An improved Gilbert multiplier is used for the synapse design. It occupies a compact area and achieves high linearity over a very large dynamic range. The input and output neurons are specially tailored to reduce the network settling time and minimize ihe silicon area that is used for implementation. The operation speed of the entire chip is above 4 MHz, which provides an equivalent computational power of tens of giga multiplications per second.